HDL Code Generation Report Summary for Full_Adder
Summary
|
Model
|
Full_Adder
|
|
Model version
|
3.0
|
|
HDL Coder version
|
24.2
|
|
HDL code generated on
|
2025-03-31 21:58:43
|
|
HDL code generated for
|
|
|
Target Language
|
VHDL
|
|
Target Directory
|
hdlsrc
|
Non-default model properties
|
Backannotation
|
on
|
|
CriticalPathEstimation
|
on
|
|
GenerateCoSimModel
|
Vivado Simulator
|
|
GeneratedModelName
|
gm_EightBitHarness
|
|
HDLSubsystem
|
Eight_bit_Braun
|
|
ProjectFolder
|
braun_bas
|
|
ResetType
|
Synchronous
|
|
SimulationTool
|
Xilinx Vivado Simulator
|
|
SynthesisTool
|
Xilinx Vivado
|
|
SynthesisToolChipFamily
|
Artix7
|
|
SynthesisToolDeviceName
|
xc7a35t
|
|
SynthesisToolPackageName
|
cpg236
|
|
SynthesisToolSpeedValue
|
-1
|
|
TargetDirectory
|
braun_bas\hdlsrc
|
|
TargetFrequency
|
100
|
|
Traceability
|
on
|
Non-default block properties
No blocks found with non-default properties.